1. Field of the Invention
The present invention relates to multiplying complex numbers with a processor.
2. Related Art
In older designs for signal processing systems (such as a Digital Subscriber Line (DSL) modem), which are in general more hardware oriented, the signal equalization process and other processes, such as performing a Fast Fourier Transform (FFT), may be performed by fixed-function logic circuits. However, such system designs are commonly hard to adapt for varying application requirements. In order to increase flexibility in modem development and application, it has become more common to use software to perform the various functions in a signal processing device. As performance levels (such as data-rates) required of such devices increase, the requirements of the software efficiently to perform individual processing tasks (such as equalization or FFT) likewise increases.
Performing complex multiplication in software is somewhat complicated to implement. Using conventional instructions (e.g., scalar multiply, add, subtract) it may take many cycles to perform complex multiplication. In some circumstances (e.g., in a DSL modem) it may be necessary to perform millions of complex multiplications every second, as part of the Fast Fourier Transform (FFT) and/or equalization processes.
The complex multiplication process can therefore represent a significant proportion of the total computational cost for a signal processing system, especially in the case of a system where one processor handles the operations for multiple independent processing channels (e.g., in a multi-line DSL modem in a central office). With increasing workloads—in respect of the increasing complexity of the signal processing protocols (e.g., the number of frequencies for which equalization may be needed, in each channel)—it becomes necessary to improve the efficiency of complex multiplication in such systems.
For these and other reasons, more efficient methods and systems for complex multiplication operations are needed.